#Tau scaling

Huawei's Tau scaling puts architecture at the center of China's AI-chip push

Huawei proposed Tau scaling, a framework focused on shorter signal paths rather than only smaller transistors. LogicFolding is planned for Kirin chips in fall and winter 2026, with Huawei claiming a density jump to 238 million transistors per square millimeter. The test is whether architecture-led gains can be validated in commercial chips amid export-control limits on advanced tools.