Chips & SemiconductorsNews
CAPACITY TEST:
Marvell Teralynx T100 Puts AI Data-Center Switching Into the Chip Race
Marvell announced planned availability of its Teralynx T100 switch chip for AI training and inference infrastructure.
The 102.4 Tbps chip is built on a 3nm process, supports up to a 512-port radix and is claimed to use 25 percent lower power than competitive solutions.
The practical test is whether data-center customers use lower-power, high-radix switching to ease latency and power constraints in larger AI clusters.
